Many integrated circuits (commonly referred to as “chips”) have more than one operational mode. For example, the chip may have a normal mode during which the chip performs the normal functions for which the chip was designed; e.g., in a memory chip, the normal mode might be to process memory access requests. In addition, the chip may have test modes in which the chip is tested to determine whether the chip is functioning properly. One test mode is commonly referred to as “burn-in”. The burn-in mode is a reliability test mode during which the chip is operated while “stressed” to a degree that is greater than expected in normal operating conditions. For example, a chip might be stressed in a burn-in test by heating the chip to a relatively high temperature while powering the chip with a relatively high supply voltage VDD. Burn-in mode is commonly used to find chips that would most likely fail after a short period of use. Hereinafter, the level or value of supply voltage VDD during normal mode will be referred to as VDDN and during burn-in mode as VDDBI.
However, burn-in modes may damage otherwise good chips that have on-chip voltage generators. In particular, some chips have on-chip voltage generators that provide a negative supply voltage used to “back-bias” a substrate so as to control the threshold voltage Vtn of N-channel field effect transistors (NFETs). This negative supply voltage is commonly referred to as the VBB supply voltage. The negative substrate supply voltage VBB together with supply voltage VDD being at the higher burn-in level VDDBI may result in some transistor devices being subjecting to voltages exceeding the devices' breakdown voltage, thereby damaging these devices. Still further, some chips also have an on-chip voltage generator providing a boosted supply voltage having a level of about a volt higher than supply voltage VDD. Thus, the boosted supply voltage can further exacerbate the breakdown voltage problem.
One conventional solution to this problem is shown in FIG. 1 in which the level of negative supply voltage VBB is adjusted to a less negative value VBBBI during burn-in mode. This scheme reduces the difference between VDDBI and VBBBI to a value that is less than the breakdown voltage of the devices in the chip.
Conventional system 10 includes a normal mode section implemented by a voltage sensing circuit (VSC) 11 and a buffer circuit 12. VSC 11 has an output lead connected to an input lead of buffer circuit 12, which has an output lead that is connected to an input lead of a multiplexer 13. VSC 11 is configured to detect whether the supply voltage VBB has reached a predetermined normal mode VBB threshold. The normal mode VBB threshold is typically set to about −VDD/2, where VDD is the value of the VDD supply voltage. When the level of negative supply voltage VBB reaches the normal mode VBB threshold, VSC 11 asserts a voltage level detect signal VLDN, which is propagated by buffer circuit 12 to multiplexer 13.
System 10 also includes a burn-in section implemented by burn-in VSC 15 and a buffer circuit 16, which is also connected to multiplexer 13. VSC 15 is configured to detect whether the level of negative supply voltage VBB has reached a predetermined burn-in mode VBB threshold. The burn-in mode VBB threshold is set to a level that is less negative than the normal mode VBB threshold. When the level of supply voltage VBB reaches the burn-in mode VBB threshold, VSC 15 asserts a voltage level detect signal VLDBI, which is propagated by buffer circuit 16 to multiplexer 13.
Multiplexer 13 has an output lead connected to a charge pump (CP) 19 and a select lead connected to receive a burn-in control signal BI. Typically, signal BI is provided from an on-chip test mode register (not shown) that is loaded by an external tester (not shown). Signal BI is asserted to configure system 10 into the burn-in mode. Alternatively, on-chip detection circuitry may be used to detect when the supply voltage is at the burn-in mode level and assert signal BI.
FIG. 2 is a timing diagram illustrative of the operation of system 10 when initially powered up. The level of supply voltage VBB is represented by a waveform 21, with control signal BI being represented by a waveform 23. Voltage level detection signals VLDN, VLDBI and VLDO are respectively represented by waveforms 25, 27 and 29. In this embodiment, VSCs 11 and 15 are voltage divider type VSCs. Consequently, signals VLDN and VLDBI are analog signals, but for clarity are shown as digital signals in FIG. 2. In this example, system 10 uses a three volt VDD supply voltage, with normal mode and burn-in mode VBB thresholds being about −1.5 volts and −1.0 volts, respectively.
Referring to FIGS. 1 and 2, in this example the chip is powered up in burn-in mode. Because initially the value of supply voltage VBB is about zero volts, VSCs 11 and 15 de-assert signals VLDN and VLDBI (i.e., at logic high levels). During the burn-in mode, signal BI is asserted (i.e., at a logic high level), thereby causing multiplexer 13 to select the output signal from buffer circuit 16. Consequently, signal VLDBI essentially serves as signal VLDO during burn-in mode. The logic high level of signal VLDO activates charge pump 19 to begin negatively increasing the level of VBB supply voltage. Thus, initially, waveform 21 has a negative slope, negatively increasing from about zero volts as indicated by arrow 211.
When the level of supply voltage VBB reaches −1.0 volts (i.e., the burn-in mode VBB threshold), VSC 15 asserts the active low signal VLDBI, thereby causing signal VLDO to transition to a logic low level, as indicated by arrows 212 and 271. The logic low level of signal VLDO de-activates charge pump 19, causing the level of supply voltage VBB to stabilize at about −1 volt as indicated by arrow 213.
Conversely, when signal BI is de-asserted to configure the chip into the normal mode, multiplexer 13 selects signal VLDN (generated by VSC 11 and buffered by buffer circuit 12) to serve as output voltage level detection signal VLDO. As described above, VSC 11 de-asserts the active low signal VLDN when the level of negative supply voltage VBB is less negative than the normal mode VBB threshold. Thus, when signal BI is de-asserted, signal VLDO is also de-asserted as indicated by arrow 231 because the normal mode VBB threshold is more negative than the burn-in mode VBB threshold. Consequently, charge pump 19 is activated, causing the level of negative supply voltage VBB to negatively increase as indicated by arrow 214.
When the level of negative supply voltage VBB reaches the normal mode VBB threshold, VSC 11 asserts signal VLDN causing signal VLDO to also be asserted, as indicated by arrows 215 and 251. As a result, charge pump 19 is de-activated, allowing the level of negative supply voltage VBB to stabilize at about the normal mode VBB threshold of about −1.5 volts as indicated by arrow 216. However, one problem with this conventional approach is that the separate burn-in section occupies a relatively large portion of chip area that could be used for other circuitry. Thus, there is a need for an approach that provides normal mode and burn-in mode VBB threshold detection while occupying minimal area on the chip.